3.10.11.10.1 SPMCSR – Store Program Memory Control and Status Register


Bit	7	6	5	4	3	2	1	0
	SPMIE			WDCE	BLBSET	PGWRT	PGERS	SELFPRGEN
Access	R/W	R	R	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 7 – SPMIE SPM Interrupt Enable

If the SPMIE bit is written to ‘1’ and the I bit in the SREG is set, the SPM ready interrupt is enabled. The SPM ready interrupt is executed as long as the SELFPRGEN bit in the SPMCSR register is cleared.

Bit 6 – Reserved Bit

This bit is reserved and read as ‘0’.

Bit 5 – Reserved Bit

This bit is reserved and read as ‘0’.

Bit 4 – WDCE Watchdog Change Enable

This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit and/or change the prescaler bits, WDCE has to be set. Once written to ‘1’, the hardware clears WDCE after four clock cycles.

Bit 3 – BLBSET Boot Lock Bit Set

If this bit is written to ‘1’ at the same time as SELFPRGEN, the next LPM instruction within three clock cycles returns lock bits or fuse bits in the destination register. The BLBSET and SELFPRGEN bits automatically clear upon completion of reading the lock bits or if no LPM instruction is executed within three CPU cycles.

Bit 2 – PGWRT Page Write

If this bit is written to ‘1’ at the same time as SELFPRGEN, the next SPM instruction within four clock cycles executes a page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGWRT bit auto-clears upon completion of a page write or if no SPM instruction is executed within four clock cycles. The CPU is stopped during the entire page write operation.

Bit 1 – PGERS Page Erase

If this bit is written to ‘1’ at the same time as SELFPRGEN, the next SPM instruction within four clock cycles executes a page erase. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGERS bit auto-clears upon completion of a page erase or if no SPM instruction is executed within four clock cycles. The CPU is stopped during the entire page write operation.

Bit 0 – SELFPRGEN Self Programming Enable

This bit enables the SPM instruction for the next four clock cycles. If set to one together with BLBSET, PGWRT or PGERS, the subsequent LPM/SPM instruction has a special meaning, as described above.

If only SELFPRGEN is written, the subsequent SPM instruction stores the value from R1:R0 in the temporary page buffer addressed by the Z pointer. The LSB of the Z pointer is ignored. The SELFPRGEN bit auto-clears upon completion of an SPM instruction or if no SPM instruction is executed within four clock cycles. During page erase and page write, the SELFPRGEN bit remains high until the operation is completed.

Name:	SPMCSR
Offset:	0x03C
Reset:	0x00