35.1 DC Characteristics

Table 35-2. Operating MIPS vs. Voltage
VDD RangeTemperature RangeMaximum CPU Clock Frequency
3.0V to 3.6V-40°C to +150°C70 MHz
Table 35-3. Thermal Operating Conditions
RatingSymbolMin.Max.Unit
High-Temperature Devices
Operating Junction Temperature RangeTJ-40+165°C
Operating Ambient Temperature RangeTA-40+150°C

Power Dissipation:

Internal Chip Power Dissipation:

PINT = VDD x (IDD – Σ IOH)

I/O Pin Power Dissipation:

I/O = Σ ({VDD – VOH} x IOH) + Σ (VOL x IOL)

PDPINT + PI/OW
Maximum Allowed Power DissipationPDMAX(TJ – TA)/θJAW
Table 35-4. Operating Voltage Specifications

Operating Conditions (unless otherwise stated):

-40°C ≤ TA ≤ +150°C for High


Param No.SymbolCharacteristicMin.Max.UnitsConditions
HDC10VDDSupply Voltage3.03.6V
HDC16VPORVDD Start Voltage 


to Ensure Internal Power-on Reset Signal

—VSSV
HDC17SVDDVDD Rise Rate


to Ensure Internal Power-on Reset Signal

0.03—V/ms0V-3V in 100 ms
HBO10VBOR(1)BOR Event on VDD Transition High-to-Low2.682.99V
Note:
  1. Device is functional at VBORMIN < VDD < VDDMIN. Analog modules (ADC and comparators) may have degraded performance. The VBOR parameter is for design guidance only and is not tested in manufacturing.
Table 35-5. Operating Current (IDD)(2)
Parameter No.Typ.(1)Max.UnitsConditions
HDC2015.030.0mA+150°C3.3V10 MIPS (N1 = 1, N2 = 5, N3 = 2, 
M = 50, FVCO = 400 MHz, 
FPLLO = 40 MHz)
HDC2116.535.0mA+150°C3.3V20 MIPS (N1 = 1, N2 = 5, N3 = 1, 
M = 50, FVCO = 400 MHz, 
FPLLO = 80 MHz)
HDC2218.540.0mA+150°C3.3V40 MIPS (N1 = 1, N2 = 3, N3 = 1, 
M = 60, FVCO = 480 MHz, 
FPLLO = 160 MHz)
HDC2325.550.0mA+150°C3.3V70 MIPS (N1 = 1, N2 = 2, N3 = 1, 
M = 70, FVCO = 560 MHz, 
FPLLO = 280 MHz)
Note:
  1. Data in the “Typ.” column are for design guidance only and are not tested.
  2. Base Run current (IDD) is measured as follows:
    • Oscillator is switched to EC+PLL mode in software
    • OSC1 pin is driven with external 8 MHz square wave with levels from 0.3V to VDD – 0.3V
    • OSC2 pin is configured as an I/O in the Configuration Words (OSCIOFNC (FOSC[2]) = 0)
    • FSCM is disabled (FCKSM[1:0] (FOSC[7:6]) = 01)
    • Watchdog Timer is disabled (FWDT[15]) = 0 and WDTCONL[15] = 0)
    • All I/O pins (except OSC1) are configured as outputs and driving low
    • No peripheral modules are operating or being clocked (defined PMDx bits are all ‘1’s)
    • JTAG is disabled (JTAGEN (FICD[5]) = 0)
    • NOP instructions are executed in while(1) loop
Table 35-6. Idle Current (IIDLE)(2)
Parameter No.Typ.(1)Max.UnitsConditions
HDC4011.020.0mA+150°C3.3V10 MIPS (N1 = 1, N2 = 5, N3 = 2,
 M = 50, FVCO = 400 MHz, 
FPLLO = 40 MHz)
HDC4111.520.0mA+150°C3.3V20 MIPS (N1 = 1, N2 = 5, N3 = 1, 
M = 50, FVCO = 400 MHz, 
FPLLO = 80 MHz)
HDC4212.525.0mA+150°C3.3V40 MIPS (N1 = 1, N2 = 3, N3 = 1, 
M = 60, FVCO = 480 MHz, 
FPLLO = 160 MHz)
HDC4314.030.0mA+150°C3.3V70 MIPS (N1 = 1, N2 = 2, N3 = 1, 
M = 70, FVCO = 560 MHz, 
FPLLO = 280 MHz)
Note:
  1. Data in the “Typ.” column are for design guidance only and are not tested.
  2. Base Idle current (IIDLE) is measured as follows:
    • Oscillator is switched to EC+PLL mode in software
    • OSC1 pin is driven with external 8 MHz square wave with levels from 0.3V to VDD – 0.3V
    • OSC2 is configured as an I/O in the Configuration Words (OSCIOFNC (FOSC[2]) = 0)
    • FSCM is disabled (FCKSM[1:0] (FOSC[7:6]) = 01)
    • Watchdog Timer is disabled (FWDT[15]) = 0 and WDTCONL[15] = 0)
    • All I/O pins (except OSC1) are configured as outputs and driving low
    • No peripheral modules are operating or being clocked (defined PMDx bits are all ‘1’s)
    • JTAG is disabled (JTAGEN (FICD[5]) = 0)
    • Flash in standby with NVMSIDL (NVMCON[12]) = 1
Table 35-7. Power-Down Current (IPD)(2)
Param
 No.CharacteristicTyp.(1)Max.UnitsConditions
HDC60Base Power-Down Current7.620.0mA+150°C3.3V
Note:
  1. Data in the “Typ.” column are for design guidance only and are not tested.
  2. Base Power-Down current (IPD) is measured as follows:
    • OSC1 pin is driven with external 8 MHz square wave with levels from 0.3V to VDD – 0.3V
    • OSC2 is configured as an I/O in the Configuration Words (OSCIOFNC (FOSC[2]) = 0)
    • FSCM is disabled (FCKSM[1:0] (FOSC[7:6]) = 01)
    • Watchdog Timer is disabled (FWDT[15]) = 0 and WDTCONL[15] = 0)
    • All I/O pins (except OSC1) are configured as outputs and driving low
    • No peripheral modules are operating or being clocked (defined PMDx bits are all ‘1’s)
    • JTAG is disabled (JTAGEN (FICD[5]) = 0)
    • The regulators are in Active mode, VREGS bit = 1 (Standby mode only valid up to +85°C)
    • The regulators are in Full-Power mode, LPWREN bit = 0 (Low-Power mode only valid up to +85°C)
Table 35-8. Doze Current (IDOZE)
Parameter No.Typ.(1)Max.Doze RatioUnitsConditions
HDC7018.530.01:2mA+150°C3.3V

70 MIPS (N = 1, N2 = 2,

N3 = 1, M = 70,

FVCO = 560 MHz,

FPLLO = 280 MHz)

15.025.01:128mA
Note:
  1. Data in the “Typ.” column are for design guidance only and are not tested.
Table 35-9. Watchdog Timer Delta Current (ΔIWDT)(1)
Parameter No.Typ.Max.UnitsConditions
HDC6128—µA+150°C3.3V
Note:
  1. The ΔIWDT current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. All parameters are characterized but not tested during manufacturing.
Table 35-10. PWM Delta Current
Parameter No.Typ.Max.UnitsConditions
HDC1008.010.0mA+150°C3.3VPWM Output Frequency = 500 kHz,
PWM Input (FPLLO = 500 MHz),
(VCO = 1000 MHz, PLLFBD = 125)
HDC1016.08.0mA+150°C3.3VPWM Output Frequency = 500 kHz,
PWM Input (FPLLO = 400 MHz),
(VCO = 400 MHz, PLLFBD = 50)
HDC1022.64.0mA+150°C3.3VPWM Output Frequency = 500 kHz,
PWM Input (FPLLO = 200 MHz),
(VCO = 200 MHz, PLLFBD = 50)
HDC1031.52.5mA+150°C3.3VPWM Output Frequency = 500 kHz,
PWM Input (FPLLO = 100 MHz),
(VCO = 100 MHz, PLLFBD = 50)
Table 35-11. ADC Delta Current(1)
Parameter No.Typ.Max.UnitsConditions
HDC1206.08.5mA+150°C3.3VTAD = 14.3 ns
 (3.5 Msps conversion rate)
Note:
  1. Shared core continuous conversion. TAD = 14.3 nS (3.5 Msps conversion rate). Listed delta currents are for only one ADC core. All parameters are characterized but not tested during manufacturing.
Table 35-12. Comparator + DAC Delta Current
Parameter No.Min.Typ.Max.UnitsConditions
HDC130—2.04.0mA+150°C3.3VFPLLO @ 500 MHz(1)
Note:

  1. Listed delta currents are for only one comparator + DAC instance. All parameters are characterized but not tested during manufacturing.

Table 35-13. Op Amp Delta Current(1)
Parameter No.Typ.Max.UnitsConditions
HDC1400.82.5mA+150°C3.3V
Note:
  1. Listed delta currents are for only one op amp instance. All parameters are characterized but not tested during manufacturing.
Table 35-14. I/O Pin Input Specifications

Operating Conditions (unless otherwise stated):

3.0V < VDD < 3.6V

-40°C < TA < +150°C for High


Param
 No.SymbolCharacteristicMin.(3)Max.(4)Units
HDI50IILInput Leakage Current(1)
I/O Pins 5V Tolerant(2)-800800nA
I/O Pins Not 5V Tolerant(2)-800800nA
MCLR-800800nA
OSCI-800800nA
Note:
  1. Negative current is defined as current sourced by the pin.
  2. See the “Pin Diagrams” section for the 5V tolerant I/O pins.
  3. VPIN = VSS.
  4. VPIN = VDD.
Table 35-15. Internal FRC Accuracy

Operating Conditions (unless otherwise stated):

3.0V < VDD < 3.6V

-40°C < TA < +150°C for High


Param
 No.CharacteristicMin.Max.Units
HF20aFRC @ 8 MHz(1)-3+3%
Note:
  1. Frequency is calibrated at +25°C and 3.3V.
Table 35-16. High-Speed Analog Comparator Module Specifications(1)

Operating Conditions (unless otherwise stated):

3.0V < VDD < 3.6V

-40°C < TA < +150°C for High

Param No.SymCharacteristicMin.Typ.(1)MaxUnitsComments
HCM09FINInput Frequency400—475MHz
Note:
  1. These parameters are for design guidance only and are not tested in manufacturing.
Table 35-17. DACx Module Specifications

Operating Conditions (unless otherwise stated):

3.0V < VDD < 3.6V

-40°C < TA < +150°C for High


Param

No.

SymbolCharacteristicMin.Typ.Max.UnitsComments
HDA03INLIntegral Nonlinearity Error-45—0LSB
HDA04DNLDifferential Nonlinearity Error-5—5LSB
HDA05EOFFOffset Error-21—21LSB
HDA06EGGain Error-41—41LSB