17.7.9 OSC48M Divider
Note: OSC48MDIV is a write-synchronized
register: OSC48MSYNCBUSY.OSC48MDIV must be checked to ensure the OSC48MDIV
synchronization is complete.
The OSC48M supports the change of frequency while running with a write to the OSC48M Divider register (OSC48MDIV.DIV). The OSC48M must be running and the OSC48M on demand bit (OSC48MCTRL.ONDEMAND) must be cleared when the OSC48MDIV.DIV is changed, to ensure synchronization is complete. The OSC48M must remain enabled until the sync busy flag returns to '0' (OSC48M SYNCBUSY.OSC48MDIV = 0).
| Name: | OSC48MDIV |
| Offset: | 0x15 |
| Reset: | 0x0B |
| Property: | PAC Write-Protection, Write-Synchronized |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DIV[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 1 | 0 | 1 | 1 | |||||
Bits 3:0 – DIV[3:0] Oscillator Divider Selection
These bits control the oscillator frequency range by adjusting the division ratio. The oscillator frequency is 48 MHz divided by DIV+1.
| Value | Description |
|---|---|
| 0b0000 | 48 MHz |
| 0b0001 | 24 MHz |
| 0b0010 | 16 MHz |
| 0b0011 | 12 MHz |
| 0b0100 | 9.6 MHz |
| 0b0101 | 8 MHz |
| 0b0110 | 6.86 MHz |
| 0b0111 | 6 MHz |
| 0b1000 | 5.33 MHz |
| 0b1001 | 4.8 MHz |
| 0b1010 | 4.36 MHz |
| 0b1011 | 4 MHz |
| 0b1100 | 3.69 MHz |
| 0b1101 | 3.43 MHz |
| 0b1110 | 3.2 MHz |
| 0b1111 | 3 MHz |