17.7.16 DPLL Synchronization Busy
| Name: | DPLLSYNCBUSY |
| Offset: | 0x2C |
| Reset: | 0x00 |
| Property: | – |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DPLLPRESC | DPLLRATIO | ENABLE | |||||||
| Access | R | R | R | ||||||
| Reset | 0 | 0 | 0 |
Bit 3 – DPLLPRESC DPLL Prescaler Synchronization Status
| Value | Description |
|---|---|
| 0 | The DPLLRESC register has been synchronized. |
| 1 | The DPLLRESC register value has changed and its synchronization is in progress. |
Bit 2 – DPLLRATIO DPLL Loop Divider Ratio Synchronization Status
| Value | Description |
|---|---|
| 0 | The DPLLRATIO register has been synchronized. |
| 1 | The DPLLRATIO register value has changed and its synchronization is in progress. |
Bit 1 – ENABLE DPLL Enable Synchronization Status
| Value | Description |
|---|---|
| 0 | The DPLLCTRLA.ENABLE bit has been synchronized. |
| 1 | The DPLLCTRLA.ENABLE bit value has changed and its synchronization is in progress. |