17.7.1 Interrupt Enable Clear
Name: | INTENCLR |
Offset: | 0x00 |
Reset: | 0x00000000 |
Property: | PAC Write-Protection |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
DPLLLDRTO | DPLLLTO | DPLLLCKF | DPLLLCKR | ||||||
Access | R/W | R/W | R/W | R/W | |||||
Reset | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
OSC48MRDY | XOSCFAIL | XOSCRDY | |||||||
Access | R/W | R/W | R/W | ||||||
Reset | 0 | 0 | 0 |
Bit 11 – DPLLLDRTO DPLL Loop Divider Ratio Update Complete Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the DPLL Loop Divider Ratio Update Complete Interrupt Enable bit, which disables the DPLL Loop Divider Ratio Update Complete interrupt.
Value | Description |
---|---|
0 | The DPLL Loop Divider Ratio Update Complete interrupt is disabled. |
1 | The DPLL Loop Divider Ratio Update Complete interrupt is enabled. |
Bit 10 – DPLLLTO DPLL Lock Timeout Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the DPLL Lock Timeout Interrupt Enable bit, which disables the DPLL Lock Timeout interrupt.
Value | Description |
---|---|
0 | The DPLL Lock Timeout interrupt is disabled. |
1 | The DPLL Lock Timeout interrupt is enabled. |
Bit 9 – DPLLLCKF DPLL Lock Fall Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the DPLL Lock Fall Interrupt Enable bit, which disables the DPLL Lock Fall interrupt.
Value | Description |
---|---|
0 | The DPLL Lock Fall interrupt is disabled. |
1 | The DPLL Lock Fall interrupt is enabled. |
Bit 8 – DPLLLCKR DPLL Lock Rise Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the DPLL Lock Rise Interrupt Enable bit, which disables the DPLL Lock Rise interrupt.
Value | Description |
---|---|
0 | The DPLL Lock Rise interrupt is disabled. |
1 | The DPLL Lock Rise interrupt is enabled. |
Bit 4 – OSC48MRDY OSC48M Ready Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the OSC48M Ready Interrupt Enable bit, which disables the OSC48M Ready interrupt.
Value | Description |
---|---|
0 | The OSC48M Ready interrupt is disabled. |
1 | The OSC48M Ready interrupt is enabled. |
Bit 1 – XOSCFAIL Clock Failure Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the XOSC Clock Failure Interrupt Enable bit, which disables the XOSC Clock Failure interrupt.
Value | Description |
---|---|
0 | The XOSC Clock Failure interrupt is disabled. |
1 | The XOSC Clock Failure interrupt is enabled. |
Bit 0 – XOSCRDY XOSC Ready Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the XOSC Ready Interrupt Enable bit, which disables the XOSC Ready interrupt.
Value | Description |
---|---|
0 | The XOSC Ready interrupt is disabled. |
1 | The XOSC Ready interrupt is enabled. |