17.7.11 OSC48M Synchronization Busy
| Name: | OSC48MSYNCBUSY |
| Offset: | 0x18 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OSC48MDIV | |||||||||
| Access | R | ||||||||
| Reset | 0 |
Bit 2 – OSC48MDIV Oscillator Divider Synchronization Status
This bit is set when OSC48MDIV register is written.
This bit is cleared when OSC48MDIV synchronization is completed.
| Value | Description |
|---|---|
| 0 | No synchronized access. |
| 1 | Synchronized access is ongoing. |