5.12.2.3 Watchdog Status Register
| Name: | WDSR |
| Offset: | 0x23 |
| Reset: | 0x0 |
| Property: | R, R/W |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OFF | CACC | ILLCON | TRIGS | OF | OFSLP | ETRIG | Reserved | ||
| Access | R | R/W | R/W | R | R/W | R/W | R/W | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – OFF
(Submit Feedback)| Value | Description |
|---|---|
| 1 | Watchdog is OFF. |
| 0 | Watchdog is ON. |
Bit 6 – CACC
(Submit Feedback)Bit 5 – ILLCON
(Submit Feedback)Bit 4 – TRIGS
(Submit Feedback)| Value | Description |
|---|---|
| 1 | The device sets this bit to ‘1’ if the Window mode watchdog is in the first half of the window. |
| 0 | The device sets this bit to ‘0’ if the Window mode watchdog is in the second half of the window. |
Bit 3 – OF
(Submit Feedback)Bit 2 – OFSLP
(Submit Feedback)Bit 1 – ETRIG
(Submit Feedback)Bit 0 – Reserved
(Submit Feedback)Reserved, do not modify reset value!
