1.3.6.1 Simulation Using Micron DDR4 SDRAM Model

To simulate the DDR4 model, perform the following steps:

  1. The PolarFire® Evaluation Kit features the DDR4 SDRAM from Micron with the MT40A1G8WE083E part number. The DDR4 simulation model files are available at the design files path mpf_an4594_df\HW\src\stimulus.
  2. To run the simulation, navigate to Design Flow > Verify Pre-Synthesized Design and double-click the Simulate option, as shown in the following figure.
    Figure 1-5. Simulating Pre-Synthesized Design

The AXI_IF block initiates 16 bursts (each burst has 16 operations of read and write) of reads and writes to DDR4 memory through the CMD_Decoder block.

The following figure shows the AXI Master signal write operation.

Figure 1-6. AXI Master Signal Write Operation

The following figure shows the DDR4 signals.

Figure 1-7. DDR4 Signals

The following figure shows the AXI Master signal read operation.

Figure 1-8. AXI Master Signal Read Operation