40.5.2.10 Initialization

The following steps are required to configure the ADC for operation:

  1. Configure input pins for operation as analog input pins, ADC_AINk.
  2. Configure a GCLK generator to provide the GCLK_ADC clock .
  3. Configure ADC registers:
    1. Copy factory-provided calibration values from the CAL OTP Register FCCFG65 into CALCTRL for all the ADC in use by the application.
    2. Configure CTRLA as needed but do not set CTRLA.ENABLE.
    3. Configure CTRLD, choosing the clock divider (CTLCKDIV) for the CTL_CLK clock based on the GCLK_ADC, Voltage Reference (VREFSEL), and Wake-up Delay Exponent (WKUPEXP).
    4. (Optionally) Enable ADC interrupts for FIFO support using CTLINTENSET. Optionally enable the interrupts for VREFRDY and Core ‘n’ ready (or these conditions can be monitored by watching CTLINTFLAG in a while(1) loop). Enable interrupt vector (ADC Global Interrupt) in the NVIC.
    5. Enable ADC interrupts using the INTENSET registers. Enable the corresponding NVIC interrupt vector.
    6. For each ADCn, configure its Control register (CORCTRLn):
      • Set the clock divider, ADCDIV, for the ADC module clock, CORE_CLK[n].
      • Set the sample count SAMC (ADCDIV and SAMC determine the ADC module’s sample rate fs).
      • If ADC resolution other than 12 bits is desired, set it using SELRES.
      • Other settings in CORCTRLn as needed.
    7. Setup differential channels using CHNCFG3n.DIFFk = 1 for signals pairs k and k+1 (k even).
    8. Select the input channels for each scan using CHNCFG2n.CSSk = 1.
    9. Set the data format for each sample using CHNCFG2n.FRACTk and CHNCFG3n.SIGNk.
    10. Setup channel triggers.
      • (Optional: Setup up the Digital Filter and Digital Comparator with the associated modules).
  4. Enable the ADC by setting CTRLA.ENABLE = 1.
  5. Wait until CTLINTFLAG.VREFRDY = 1, either using an ISR or polling in a while(1) loop. This signals that the chip’s analog environment is ready.
  6. Wait for CRRDYn to go high in CTLINTFLAG, indicating that the corresponding ADC module is ready. This can be polled in a while(1) loop or trapped by the ISR attached to the ADC Global Interrupt.