40.5.2.3 Clocks Setup

The interface to the Advanced Peripheral Bus (APB) is clocked by the system’s Main Clock.

The ADC Core can change the provided GCLK to obtain a maximum frequency ≤72Mhz. The Peripheral Channel Control Register PCHCTRLn selects the GCLK generator. The register PCHCTRL[n].GEN[m] is configured to select the GCLK’s clock generator to be used for the ADC. The resulting ADC Control Clock is referred to as CTL_CLK in this chapter.

See GCLK Peripheral Channel Control Mapping and Peripherals Configuration Summary for a full peripheral index listing. The generator listing can be found in the Peripheral Dependencies table.

This register selects the input clock for the generator and provides the clock divider to divide an input clock down to the clock output of GCLK Generator m.