40.5.2.1 Enabling, Disabling, and Resetting

The ADC is enabled by setting CTRLA.ENABLE = 1. Setting this bit to zero disables the ADC. The ADC can be reset by setting CTRLA.SWRST = 1 to initiate a software reset (The ADC module is reset when the SYNCBUSY.SWRST bit goes low).

The steps to enable the ADC are defined in the Initialization section.

The analog bias in each of the ADC SAR Cores can be powered-up or powered-down individually by setting or resetting the corresponding CTRLD.ANLENx bit.

Each ADC SAR Core x has a built-in warm-up counter, which will not allow any trigger to propagate for a warm-up period (typically 20 us). This period occurs when the core is enabled or re-enabled.

Note: The analog circuitry must be turned on before the digital circuitry.

The individual CHNENx bits can be used to provide a finer control of the power consumption of the entire ADC module, but they do not control the enabling of the analog and bias circuitry in the ADC Analog IP.

A device reset forces all registers to their reset state. This forces the A/D module to be turned off, and any conversion or sampling sequence is aborted. The bandgap reference circuit is also turned off, therefore the ADC resuming operations will have to wait for the bandgap reference circuit to stabilize by polling (or requesting to be interrupted by) CTLINTFLAG.VREFRDY Status bit.

If the ADC is stopped during Debug mode, it is handled by simply resetting the ADC module state machines. This is accomplished by forcing all the internal channel enable signals CTRLD.CHNENx to zero. The CTRLA.ENABLE should stay high, which will enable all the core_clk[x], x = 0...(ACN-1), to remain active and keep all the analog biasing circuits alive.

Note: The DBGCTRL.DBGRUN bit is unchanged by a software reset.