40.5.2.4 Conversion Timing and Sampling Rate

If the period of CTL_CLK is T_Q, then the period of the respective ADC_CLK module clock, T_AD, is given by:

T_AD = 2·ADCDIV·T_Q.

The minimum ADC clock period is T_AD = 2·T_Q.

Provided CTRLB.SWCNVEN = 0:

The maximum ADC throughput rate for the ADC module with N_BITS of resolution is given below:

Maximum Throughput rate F_TPR = [ 1/ [(CORCTRL.SAMC+2)TAD + (N_BITS+1)TAD] ] / #Active ADC Channels

Example:

(CORCTRL.SAMC = 0x1, 12-bit resolution and 2 AINx scan channels selected)

F_TPR = [ 1/ (3TAD + 13TAD) ] / 2 = (1 / 16TAD) / 2