40.5.2.11 Channel Triggers

The ADC Controller needs to know when a channel requests an analog-to-digital conversion. This is done by way of a channel “trigger” which starts the capture and conversion for the associated input channel. The trigger signal is passed by the channel to the module’s Access Arbiter. The Access Arbiter drives the address selections to both the input Analog Multiplexer and to the output Digital De-multiplexer.

Trigger Priority

The Access Arbiter evaluates all the asserted triggers just before updating the input active channel selection and chooses the winning trigger, which is the trigger associated with the ADC Channel having the lowest rank number (id). For example, the highest priority for ADC SAR Core1 is ADC Channel 0 (zero) and the lowest priority ADC Channel is channel 15 (fifteen, assuming 16 channels are implemented). Priority is decreasing with the increasing channel ID number. This is referred to as the inverse natural priority order.

When two triggers arrive at the Access Arbiter at the same time the trigger associated with the input channel having the lower index k will be serviced. The second trigger will be queued for later service, provided it is not overwritten by a third trigger request. In that case, the third trigger will be lost and not serviced.

Note: A scan can involve many channels that require sequential conversion. This prevents other possible higher priority triggers from being serviced. To prevent long delays, the priority for the scan trigger is ranked the lowest among all triggers by the Access Arbiter. This means that if another trigger arrives for an ADC Channel not included in the scan list, that ADC Channel will gain priority to interrupt the scan execution and have its conversion serviced by the ADC SAR Core right away. Serving an other request can cause a scan delay that may affect the accuracy of the result because the multiple samples will not be contiguous.

The user should arrange a scan to occur while there are no expected interruptions from higher priority ADC conversion requests.

Channel Trigger Selection

The trigger used for the ADC, Input Channel k, is specified by CHNCFG{4|5}n.TRGSRCk[3:0]. (CHNCFG4n contains the trigger choices for k = 0,1,…,7. CHNCFG5n contains the trigger choices for k = 8,9,…,15. TRGSRCk for Sn ≤ k are not defined.)

The possible selections for TRGSRCk are as follows:

0000 = No trigger (NOP)

0001 = Global Software Trigger (CTRLB.GSWTRG)

0010 = Global Level Software Trigger (CTRLB.LSWTRG)

0011 = SCANTRG - Scan Trigger

0100 = STRIG Synchronous Trigger

0101 - 1111 = ADC Trigger Event User 0 – 10

Input channels with no assigned triggers (NOP) temporarily disables that analog channel from being converted.

For all trigger sources except the SCANTRG, setting the TRGSRCk will result in only input channel k being serviced by the ADC. To collect a group of samples, or “scan,” of input channels set TRGSRCk to SCANTRG. The source for the Scan Trigger (SCANTRG) is selected with CORCTRLn.STRGSRC (see below). All the input channels to be included in a scan started by SCANTRG must have CHNCFG2n.CSSk set to one.

The SCANTRG source is selected by CORCTRLn.STRGSRC as follows:

0000 = No trigger (NOP)

0001 = Global Software trigger (CTRLB.GSWTRG)

0010 = Level Software trigger (CTRLB.LSWTRG)

0011 = Reserved

0100 = Synchronous Trigger (STRIG)

0101 - 1111 = EVSYS Event Generator 0 – 10

The Synchronous Trigger (STRIG) is driven by a counter at the ADC Control Clock (CTL_CLK) frequency and fires when the counter reaches the value defined by the trigger source delay counter (CTRLC.CNT[15:0]). To enable this trigger, set CTRLB.STRGEN = 1.

Software Triggers

The Configuration and Status Registers (CSR) generates software controlled trigger source signals into the Trigger Sources Multiplexer, to allow the CPU to initiate ADC conversions under software control by means of writes to CSRs.

ADC captures can be directly controlled from software by using the Global Software Trigger to start a single capture (when CTRLB.GSWTRG = 1) or by using the Global Level Software Trigger to start a burst of captures that will continue as long as CTRLB.LSWTRG = 1 and stop when LSWTRG = 0.

ADC Debugging

The register setting for Software-controlled Conversion Enable (SWCNVEN) allows two bits in CTRLB to manually control the ADC module’s input channel. When CTRLB.SWCNVEN = 1, CTRLB.ADCHSEL selects the ADC input to be sampled. For this to work all the other input channels for the module must be disabled by setting CHNCFG{4|5}n.TRGSRCk = 0. Setting TRGSRCk can only be accomplished when the ADC is disabled. Sampling of the specified input channel starts when CTRLB.SAMP is set to one and stops when CTRLB.SAMP is reset to zero. Set CTRLB.RQCNVRT = 1 to trigger an individual channel conversion.

Note: The SYNCBUSY register controls access to the CTRLA and CTRLB registers during synchronization. After writing to the CTRLB register, the SYNCBUSY.CTRLB value will go high. Wait until the hardware sets this bit low (indicating that synchronization has completed) before attempting to write to the CTRLB register again.

Trigger Limitations

  • Trigger Rule 1: In order to ensure synchronizing of every single pulse created by the Global Software Trigger (GSWTRG), the GSWTRG pulses must be at least 4 ADC Control Clock periods apart, positive edge to positive edge. This because the GSWTRG lasts only 1 single APB clock period.
  • Trigger Rule 2: The user is allowed to execute a Scan Sequence with no channels selected for the sequence. This means that when all the channels n associated to the scan trigger STRIGk (by CHNCFG{4|5}n.TRGSRCk[3:0] = 4b0011, SCANTRG) have their CHNCFG2n.CSSk = 0, the end-of-scan flag INTFLAGn.EOSRDY will immediately be set to 1 because the scan cycle cannot be busy, since it is empty.
  • Trigger Rule 3: If a channel k is effectively included in scan n by setting CHNCFG{4|5}n.TRGSRCk[3:0] = 4b0011 (SCANTRG) and CHNCFG2n.CSSk = 1, then the user MUST ensure that NO other triggers are generated for that channel, such as using CTRLB.RQCNVRT or any digital filter. Otherwise the scan behavior is unpredictable.
  • Trigger Rule 4: In order to ensure synchronizing of every single pulse created by the Level Global Software Trigger (LSWTRG), the LSWTRG pulses must be at least 8 ADC Control Clock periods + 10 Main Clock clock periods positive edge to positive edge. It must also be at least 4 ADC control clock periods + 4 Main Clock periods negative edge to positive edge.