4.3.4.2 Zero-Delay Buffer

Zero-delay buffer provides a phase-aligned copy of the input clock at the output pins and is useful for clock distribution applications that require a single clock to be fanned out to multiple external components with low skew between them.

As shown in the following figure, the PLL can be used to create a zero-delay clock buffer. The PLL is configured in external feedback mode and the feedback path is confined to the preferred PLL output pin. The zero-delay buffer aligns the clock driven off-chip with the clock input for a minimal delay between the clock input and the external clock output. Delay lines are provided in the CCC to allow the output clock to be pulled back in time.

To create a zero-delay buffer, the routing delay between the CLK_OUT pin and the external component clock input pin must match the routing delay between the CLK_OUT pin and the PLL feedback clock pin. It is recommended to use the preferred PLL output pin to route the clock output off-chip and the preferred clock input pins to connect the PLL reference and feedback clock to reduce clock injection delay.

The clock at the internal register can lead or lag the external clock output.