20.3.7 SENTx Receive Data Register High

Note:

Register bits are read-only in Receive mode (RCVEN = 1). In Transmit mode, the CRC[3:0] bits are read-only when automatic CRC calculation is enabled (RCVEN = 0, CRCEN = 1).

Name:	SENTxDATH
Offset:	0x96, 0xAE


Bit	15	14	13	12	11	10	9	8
	STAT[3:0]				DATA1[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	DATA2[3:0]				DATA3[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 15:12 – STAT[3:0] Status Nibble Data bits⁽¹⁾

Bits 11:8 – DATA1[3:0] Data Nibble 1 Data bits⁽¹⁾

Bits 7:4 – DATA2[3:0] Data Nibble 2 Data bits⁽¹⁾

Bits 3:0 – DATA3[3:0] Data Nibble 3 Data bits⁽¹⁾

DS70005452D

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