20.3.6 SENTx Receive Data Register Low

Note:

Register bits are read-only in Receive mode (RCVEN = 1). In Transmit mode, the CRC[3:0] bits are read-only when automatic CRC calculation is enabled (RCVEN = 0, CRCEN = 1).

Name:	SENTxDATL
Offset:	0x94, 0xAC


Bit	15	14	13	12	11	10	9	8
	DATA4[3:0]				DATA5[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	DATA6[3:0]				CRC[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 15:12 – DATA4[3:0] Data Nibble 4 Data bits⁽¹⁾

Bits 11:8 – DATA5[3:0] Data Nibble 5 Data bits⁽¹⁾

Bits 7:4 – DATA6[3:0] Data Nibble 6 Data bits⁽¹⁾

Bits 3:0 – CRC[3:0] CRC Nibble Data bits⁽¹⁾

DS70005452D

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