20.3.5 SENTx Sync Period Timer Register

Note:

These register bits are not available in Transmit mode (RCVEN = 0).

Name:	SENTxSYNC
Offset:	0x90, 0xA8


Bit	15	14	13	12	11	10	9	8
	SENTSYNC[15:8]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	SENTSYNC[7:0]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0

Bits 15:0 – SENTSYNC[15:0] Captured Sync Period bits⁽¹⁾

In Receive mode, the length of the synchronization time period is captured.

DS70005452D

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