10.2.3.4 DMA High Address Limit Register

Name:	DMAH
Offset:	0xAAE


Bit	15	14	13	12	11	10	9	8
	HADDR[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	1	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	HADDR[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 15:0 – HADDR[15:0] DMA High Address Limit bits

DS70005452D

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.