28.1.7 DMT Hold Register⁽¹⁾

Note:

The DMTHOLDREG register is initialized to ‘0’ on Reset, and is only loaded when the DMTCNTL and DMTCNTH registers are read.

Name:	DMTHOLDREG
Offset:	0x070


Bit	15	14	13	12	11	10	9	8
	UPRCNT[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	UPRCNT[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 15:0 – UPRCNT[15:0] DMTCNTH Register Value when DMTCNTL and DMTCNTH were Last Read bits

DS70005452D

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