28.1.2 Deadman Timer Preclear Register
| Name: | DMTPRECLR |
| Offset: | 0x060 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| STEP1[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | |||||||||
| Reset |
Bits 15:8 – STEP1[7:0] DMT Preclear Enable bits
| Value | Description |
|---|---|
| 01000000 | Enables the Deadman Timer preclear (Step 1) |
| All Other Write Patterns | Sets the BAD1 flag; these bits are cleared when a DMT Reset event occurs. STEP1[7:0] bits are also cleared if the STEP2[7:0] bits are loaded with the correct value in the correct sequence. |