14.13.1 INTCON

Interrupt Control Register

Important: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software must ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt. This feature allows for software polling.

Name:	INTCON
Offset:	0xFF2


Bit	7	6	5	4	3	2	1	0
	GIE/GIEH	PEIE/GIEL	IPEN		INT3EDG	INT2EDG	INT1EDG	INT0EDG
Access	R/W	R/W	R/W		R/W	R/W	R/W	R/W
Reset	0	0	0		0	1	1	1

Bit 7 – GIE/GIEH Global Interrupt Enable bit

Value	Name	Description
1	If IPEN = `1`	Enables all unmasked interrupts and cleared by hardware for high-priority interrupts only
0	If IPEN = `1`	Disables all interrupts
1	If IPEN = `0`	Enables all unmasked interrupts and cleared by hardware for all interrupts
0	If IPEN = `0`	Disables all interrupts

Bit 6 – PEIE/GIEL Peripheral Interrupt Enable bit

Value	Name	Description
1	If IPEN = `1`	Enables all low-priority interrupts and cleared by hardware for low-priority interrupts only
0	If IPEN = `1`	Disables all low-priority interrupts
1	If IPEN = `0`	Enables all unmasked peripheral interrupts
0	If IPEN = `0`	Disables all peripheral interrupts

Bit 5 – IPEN Interrupt Priority Enable bit

Value	Description
1	Enable priority levels on interrupts
0	Disable priority levels on interrupts

Bits 0, 1, 2, 3 – INTxEDG External Interrupt ‘x’ Edge Select bit

Value	Description
1	Interrupt on rising edge of INTx pin
0	Interrupt on falling edge of INTx pin

Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software must ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt. This feature allows for software polling.