14.13.27 IPR5

Peripheral Interrupt Priority Register 5

Name:	IPR5
Offset:	0xE24


Bit	7	6	5	4	3	2	1	0
	TMR8IP	TMR7IP	TMR6IP	TMR5IP	TMR4IP	TMR3IP	TMR2IP	TMR1IP
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	1	1	1	1	1	1	1	1

Bit 7 – TMR8IP TMR8 to PR8 Match Interrupt Priority bit

Value	Description
1	High priority
0	Low priority

Bit 6 – TMR7IP TMR7 to PR7 Match Interrupt Priority bit

Value	Description
1	High priority
0	Low priority

Bit 5 – TMR6IP TMR6 to PR6 Match Interrupt Priority bit

Value	Description
1	High priority
0	Low priority

Bit 4 – TMR5IP TMR5 to PR5 Match Interrupt Priority bit

Value	Description
1	High priority
0	Low priority

Bit 3 – TMR4IP TMR4 to PR4 Match Interrupt Priority bit

Value	Description
1	High priority
0	Low priority

Bit 2 – TMR3IP TMR3 to PR3 Match Interrupt Priority bit

Value	Description
1	High priority
0	Low priority

Bit 1 – TMR2IP TMR2 to PR2 Match Interrupt Priority bit

Value	Description
1	High priority
0	Low priority

Bit 0 – TMR1IP TMR1 to PR1 Match Interrupt Priority bit

Value	Description
1	High priority
0	Low priority

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