14.13.5 PIR3
| Name: | PIR3 |
| Offset: | 0xE36 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RC2IF | TX2IF | RC1IF | TX1IF | BCL2IF | SSP2IF | BCL1IF | SSP1IF | ||
| Access | R | R | R | R | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 5, 7 – RCxIF EUSARTx Receive Interrupt Flag bit
| Value | Description |
|---|---|
| 1 | The EUSARTx receive buffer, RCxREG, is full (cleared by reading RCxREG) |
| 0 | The EUSARTx receive buffer is empty |
Bits 4, 6 – TXxIF EUSARTx Transmit Interrupt Flag bit
| Value | Description |
|---|---|
| 1 | The EUSARTx transmit buffer, TXxREG, is empty (cleared by writing TXxREG) |
| 0 | The EUSARTx transmit buffer is full |
Bits 1, 3 – BCLxIF MSSPx Bus Collision Interrupt Flag bit
| Value | Description |
|---|---|
| 1 | A bus collision has occurred while the MSSPx module configured in I2C host was transmitting (must be cleared in software) |
| 0 | No bus collision occurred |
Bits 0, 2 – SSPxIF Synchronous Serial Port ‘x’ Interrupt Flag bit
| Value | Description |
|---|---|
| 1 | The transmission/reception is complete (must be cleared in software) |
| 0 | Waiting to transmit/receive |