32.7.10 ADACQ

ADC Acquisition Time Control Register

Name:	ADACQ
Offset:	0xF5C


Bit	7	6	5	4	3	2	1	0
	ADACQ[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 7:0 – ADACQ[7:0] Acquisition (charge share time) Select bits

Table 32-7.
ADACQ	Acquisition Time
ADACQ	ADCS != F_RC	ADCS = F_RC
255	255 clock of F_OSC	255 clock of F_RC
254	254 clock of F_OSC	254 clock of F_RC
...	...
2	2 clock of F_OSC	2 clock of F_RC
1	1 clock of F_OSC	1 clock of F_RC
0	Not included in the data conversion cycle⁽¹⁾

Note:

If ADPRE is not equal to ‘0’, then ADACQ = 0b0000_0000 means Acquisition Time is 256 clocks of F_OSC or F_RC.

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