5.1.3 A_ADDR and B_ADDR

14 bits are required to address the 16K independent locations in x1 mode. In wider modes, fewer address bits are used. The required bits are MSb justified and unused LSb bits must be tied to 0. A_ADDR is synchronized by A_CLK, while B_ADDR is synchronized to B_CLK. Two-port mode is in effect when the width of at least one port is greater than 20, and A_ADDR provides the read-address while B_ADDR provides the write-address. The following table lists the address buses for the two ports.