5.1.8 A_CLK and B_CLK
(Ask a Question)All signals in ports A and B are synchronous to the corresponding port clock. All addresses, data, block-port select, write-enable, and read-enable inputs must be set up before the rising edge of the clock. The read or write operation begins with the rising edge. Two-port mode is in effect when the width of at least one port is greater than 20 bits, and A_CLK provides the read clock while B_CLK provides the write clock.