2.1.2.6 Read Operation

In two-port mode, LSRAM supports both pipelined and non-pipelined read operations. In a pipelined read operation, the output data is registered at the pipeline registers making the data available on the corresponding data output on the next clock cycle. If the ECC pipeline mode is enabled, an additional clock cycle is required for read data output. ECC flags are valid in the same clock cycle as the output data. For more information, see ECC Mode (For x33 Two-Port Mode Only).

In non-pipelined read operations, the pipeline registers are bypassed and read data is available on the output port in the same clock cycle. During this operation, LSRAM can generate glitches on the data output buses. Therefore, it is recommended to use LSRAM with pipeline registers to avoid glitches.

The following figure shows the timing for both pipelined and non-pipelined read operations in two-port mode.