2.1.2.5 ECC Mode (For x33 Two-Port Mode Only)
(Ask a Question)In the Two-Port mode, when the port width is set to x33, ECC (single-bit error correction and dual-bit error detection) is available. The ECC encoder provides 40 bits (33 data bits and 7 encoded data bits) of data in the x33 mode (the seven encoded bits are not accessible to the user). Single-bit and dual-bit errors are counted for a full 33-bit read data word.
The ECC decoder contains an optional pipeline register that adds a clock cycle of latency to the read operation (including the flags). As the output data can also be pipelined, there are four possible scenarios:
- Pipeline mode with non-pipelined ECC
- Pipeline mode with pipelined ECC
- Non-Pipeline mode with non-pipelined ECC
- Non-Pipeline mode with pipelined ECC
The following table lists the two flags generated by the ECC logic.
| ECC Errors | SB_CORRECT | DB_DETECT | Correction |
|---|---|---|---|
| No error | 0 | 0 | NA |
| Single-bit error | 1 | 0 | Correction |
| Double-bit or Multi-bit error | 1 | 1 | No correction |
Any multiple bit errors greater than one has both flags asserted, and the 33-bit read data word not corrected. No scrubbing is done inside the LSRAM when ECC decoder detects any bit errors. All scrubbing must be done in the fabric design. ECC simulation is not supported.
In the Pipeline mode, these flags are valid only in the read data output clock cycle. In Non-Pipeline mode, the ECC flags are valid only in the same clock cycle as the corresponding read data output, as the flags are reset in the next clock cycle.
In SmartDebug, the ECC bits are included in the 40 bits data divided between adjacent locations. 16 bits of data in one location and 17 bits of data in the next location, the remaining 5 bits are ECC bits. The ECC bits are pre-calculated by Libero SoC and loaded in the background with the SRAM initialization data. For information about loading the initializing client for the SRAM memory IP in Libero SoC, see PolarFire Family Power-Up and Resets User Guide .