37.7.5 CVD Results NEG FIFO Read Register
Name: | CVDRESL |
Offset: | 0x014 |
Reset: | 0x00000000 |
Property: | - |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
NEG[18:16] | |||||||||
Access | R | R | R | ||||||
Reset | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
NEG[15:8] | |||||||||
Access | R | R | R | R | R | R | R | R | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
NEG[7:0] | |||||||||
Access | R | R | R | R | R | R | R | R | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 18:0 – NEG[18:0]
The accumulated result of the negative-side measurements. The controller supports up to 128x oversampling; therefore, each polarity can accumulate up to 18 bits when using 12-bit ADC (actual number of bits = ADCBITS + 7). The accumulation is not shifted back down to create an average. Therefore, if oversampling was requested, the software will need to account for the left-shift of the result returned.