40.8.19 SDHC Normal Interrupt Status Enable Register: e.MMC
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | NISTER |
| Offset: | 0x34 |
| Reset: | 0x0000 |
| Property: | - |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| BOOTAR | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CREM | CINS | BRDRDY | BWRRDY | DMAINT | BLKGE | TRFC | CMDC | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 14 – BOOTAR Boot Acknowledge Received Status Enable
Note: This register entry is specific to the e.MMC operation mode.
| Value | Name | Description |
|---|---|---|
| 0 | MASKED | The BOOTAR status flag in SDHC_NISTR is masked. |
| 1 | ENABLED | The BOOTAR status flag in SDHC_NISTR is enabled. |
Bit 7 – CREM Card Removal Status Enable
| Value | Name | Description |
|---|---|---|
| 0 | MASKED | The CREM status flag in SDHC_NISTR is masked. |
| 1 | ENABLED | The CREM status flag in SDHC_NISTR is enabled. |
Bit 7 – CINT Card Interrupt Status Enable
If this bit is set to 0, the peripheral clears interrupt requests to the system. The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. The user may clear this bit before servicing the Card Interrupt and may set this bit again after all interrupt requests from the card are cleared to prevent inadvertent interrupts.
| Value | Name | Description |
|---|---|---|
| 0 | MASKED | The CINT status flag in SDHC_NISTR is masked. |
| 1 | ENABLED | The CINT status flag in SDHC_NISTR is enabled. |
Bit 6 – CINS Card Insertion Status Enable
| Value | Name | Description |
|---|---|---|
| 0 | MASKED | The CINS status flag in SDHC_NISTR is masked. |
| 1 | ENABLED | The CINS status flag in SDHC_NISTR is enabled. |
Bit 5 – BRDRDY Buffer Read Ready Status Enable
| Value | Name | Description |
|---|---|---|
| 0 | MASKED | The BRDRDY status flag in SDHC_NISTR is masked. |
| 1 | ENABLED | The BRDRDY status flag in SDHC_NISTR is enabled. |
Bit 4 – BWRRDY Buffer Write Ready Status Enable
| Value | Name | Description |
|---|---|---|
| 0 | MASKED | The BWRRDY status flag in SDHC_NISTR is masked. |
| 1 | ENABLED | The BWRRDY status flag in SDHC_NISTR is enabled. |
Bit 3 – DMAINT DMA Interrupt Status Enable
| Value | Name | Description |
|---|---|---|
| 0 | MASKED | The DMAINT status flag in SDHC_NISTR is masked. |
| 1 | ENABLED | The DMAINT status flag in SDHC_NISTR is enabled. |
Bit 2 – BLKGE Block Gap Event Status Enable
| Value | Name | Description |
|---|---|---|
| 0 | MASKED | The BLKGE status flag in SDHC_NISTR is masked. |
| 1 | ENABLED | The BLKGE status flag in SDHC_NISTR is enabled. |
Bit 1 – TRFC Transfer Complete Status Enable
| Value | Name | Description |
|---|---|---|
| 0 | MASKED | The TRFC status flag in SDHC_NISTR is masked. |
| 1 | ENABLED | The TRFC status flag in SDHC_NISTR is enabled. |
Bit 0 – CMDC Command Complete Status Enable
| Value | Name | Description |
|---|---|---|
| 0 | MASKED | The CMDC status flag in SDHC_NISTR is masked. |
| 1 | ENABLED | The CMDC status flag in SDHC_NISTR is enabled. |