40.8.40 SDHC Capabilities Control Register
Symbol | Description | Symbol | Description | Symbol | Description |
---|---|---|---|---|---|
R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
K | Write to clear | S | Software settable bit | — | — |
Name: | CACR |
Offset: | 0x230 |
Reset: | 0x00000000 |
Property: | - |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
KEY[7:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
CAPWREN | |||||||||
Access | R/W | ||||||||
Reset | 0 |
Bits 15:8 – KEY[7:0] Key
Value | Name | Description |
---|---|---|
46h | KEY |
Writing any other value in this field aborts the write operation of the CAPWREN bit. Always reads as 0. |
Bit 0 – CAPWREN Capabilities Write Enable
This bit can only be written if KEY correspond to 46h.
Value | Description |
---|---|
0 |
Capabilities registers (SDHC_CA0R and SDHC_CA1R) cannot be written. |
1 |
Capabilities registers (SDHC_CA0R and SDHC_CA1R) can be written. |