40.8.10 Host Control 1 Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | HC1R |
| Offset: | 0x28 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CARDDSEL | CARDDTL | EXTDW | DMASEL[1:0] | HSEN | DW | LEDCTRL | |||
| Access | R/W | R/W | R/W | - | - | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – CARDDSEL Card Detect Signal Selection
This bit selects the source for the card detection.
| Value | Description |
|---|---|
| 0 |
The SDHC_CD pin is selected. |
| 1 |
The Card Detect Test Level (CARDDTL) is selected (for test purpose). |
Bit 6 – CARDDTL Card Detect Test Level
This bit is enabled while the Card Detect Signal Selection (CARDDSEL) is set to 1 and it indicates whether the card is inserted or not.
| Value | Description |
|---|---|
| 0 |
No card. |
| 1 |
Card inserted. |
Bit 5 – EXTDW Extended Data Width
This bit controls the 8-bit Bus Width mode for embedded devices. Support of this function is indicated in 8-bit Support for Embedded Device in SDHC_CA0R. If a device supports the 8-bit mode, this may be set to 1. If this bit is 0, the bus width is controlled by Data Width (DW).
Bits 4:3 – DMASEL[1:0] DMA Select
One of the supported DAM modes can be selected. The user must check support of DMA modes by referring the SDHC_CA0R. Use of selected DMA is determined by DMA Enable (DMAEN) in SDHC_TMR.
| Value | Name | Description |
|---|---|---|
| 0 | SDMA |
SDMA is selected |
| 1 | Reserved |
Reserved |
| 2 | ADMA32 |
32-bit Address ADMA2 is selected |
| 3 | Reserved |
Reserved |
Bit 2 – HSEN High Speed Enable
Before setting this bit, the user must check the High Speed Support (HSSUP) in SDHC_CA0R.
If this bit is set to 0 (default), the peripheral outputs CMD line and DAT lines at the falling edge of the SD clock (up to 25 MHz). If this bit is set to 1, the SDMMC outputs the CMD line and the DAT lines at the rising edge of the SD clock (up to 50 MHz).
If Preset Value Enable (PVALEN) in SDHC_HC2R is set to 1, the user needs to reset SD Clock Enable (SDCLKEN) before changing this bit to avoid generating clock glitches. After setting this bit to 1, the user sets SDCLEN to 1 again.
| Value | Description |
|---|---|
| 0 |
Normal Speed mode. |
| 1 |
High Speed mode. Note: 1. This bit is effective only if SDHC_MC1R.DDR is set to 0. 2. The clock divider (DIV) in SDHC_CCR must be set to a value different from 0 when HSEN is 1. |
Bit 1 – DW Data Width
This bit selects the data width of the peripheral. It must be set to match the data width of the card.
| Value | Name | Description |
|---|---|---|
| 0 | 1_BIT | 1-bit mode |
| 1 | 4_BIT | 4-bit mode |
Bit 0 – LEDCTRL LED Control
This bit is used to caution the user not to remove the card while it is being accessed. If the software is going to issue multiple commands, this bit is set to 1 during all transactions.
| Value | Name | Description |
|---|---|---|
| 0 | OFF | LED off |
| 1 | ON | LED on |