40.8.2 Block Size Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | BSR |
| Offset: | 0x04 |
| Reset: | 0x0000 |
| Property: | - |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| BOUNDARY[2:0] | BLKSIZE[9:8] | ||||||||
| Access | - | - | - | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BLKSIZE[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 14:12 – BOUNDARY[2:0] SDMA Buffer Boundary
This field specifies the size of the contiguous buffer in the system memory. The SDMA transfer waits at every boundary specified by this field and the peripheral generates the DMA Interrupt to instruct the software to update SDHC_SSAR. If this field is set to 0 (buffer size = 4 Kbytes), the lowest 12 bits of SDHC_SSAR.ADDRESS point to data in the contiguous buffer, and the upper 20 bits point to the location of the buffer in the system memory. This function is active when the DMA Enable bit in the Transfer Mode Register (SDHC_TMR.DMAEN) is '1'.
| Value | Name | Description |
|---|---|---|
| 0 | 4K |
4-Kbyte boundary |
| 1 | 8K |
8-Kbyte boundary |
| 2 | 16K |
16-Kbyte boundary |
| 3 | 32K |
32-Kbyte boundary |
| 4 | 64K |
64-Kbyte boundary |
| 5 | 128K |
128-Kbyte boundary |
| 6 | 256k |
256-Kbyte boundary |
| 7 | 512K |
512-Kbyte boundary |
Bits 9:0 – BLKSIZE[9:0] Transfer Block Size
This field specifies the block size of data transfers for CMD17, CMD18, CMD24, CMD25 and CMD53. Values ranging from 1 to SDMMC_MAX_BLOCK_SIZE can be set. It can be accessed only if no transaction is executing (i.e., after a transaction has stopped). Read operations during transfers may return an invalid value, and write operations are ignored.