40.8.14 SDHC Clock Control Register

Table 40-15. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: CCR
Offset: 0x2C
Reset: 0x0000
Property: -

Bit 15141312111098 
 SDCLKFSEL[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 USDCLKFSEL[1:0]CLKGSEL  SDCLKENINTCLKSINTCLKEN 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bits 15:8 – SDCLKFSEL[7:0] SDCLK Frequency Select

This register is used to select the frequency of the SDCLK pin. There are two SDCLK Frequency modes according to Clock Generator Select (CLKGSEL).

The length of the clock divider (DIV) is extended to 10 bits (DIV[9:8] = USDCLKFSEL, DIV[7:0] = SDCLKFSEL)

– 10-bit Divided Clock Mode (CLKGSEL = 0):

FSDCLK=FBASECLK/2×DIV

. If DIV = 0 then

FSDCLK=FBASECLK

– Programmable Clock Mode (CLKGSEL = 1):

FSDCLK=FMULTCLK/DIV+1

This field depends on the setting of Preset Value Enable (PVALEN) in SDHC_HC2R.

If SDHC_HC2R.PVALEN = 0, this field is set by the user.

If SDHC_HC2R.PVALEN = 1, this field is automatically set to a value specified in one of the SDHC_PVR.

Bits 7:6 – USDCLKFSEL[1:0] Upper Bits of SDCLK Frequency Select

These bits expand the SDCLK Frequency Select (SDCLKFSEL) to 10 bits. These two bits are assigned to bit 09-08 of the clock divider as described in SDCLKFSEL.

Bit 5 – CLKGSEL Clock Generator Select

This bit is used to select the clock generator mode in the SDCLK Frequency Select field. If the Programmable mode is not supported (SDHC_CA1R.CLKMULT (Clock Multiplier) set to 0), then this bit cannot be written and is always read at 0.

This bit depends on the setting of Preset Value Enable (PVALEN) in SDHC_HC2R.

If SDHC_HC2R.PVALEN = 0, this bit is set by the user.

If SDHC_HC2R.PVALEN = 1, this bit is automatically set to a value specified in one of the SDHC_PVRx.

ValueDescription
0

Divided Clock mode (BASECLK is used to generate SDCLK).

1

Programmable Clock mode (MULTCLK is used to generate SDCLK).

Bit 2 – SDCLKEN SD Clock Enable

The peripheral stops the SD Clock when writing this bit to 0. SDCLK Frequency Select (SDCLKFSEL) can be changed when this bit is 0. Then, the peripheral maintains the same clock frequency until SDCLK is stopped (Stop at SDCLK=0). If Card Inserted (CARDINS) in SDHC_PSR is cleared, this bit is also cleared.

ValueDescription
0

SD Clock disabled

1

SD Clock enabled

Bit 1 – INTCLKS Internal Clock Stable

This bit is set to 1 when the SD clock is stable after setting SDHC_CCR.INTCLKEN (Internal Clock Enable) to 1. The user must wait to set SD Clock Enable (SDCLKEN) until this bit is set to 1.

ValueDescription
0

Internal clock not ready

1

Internal clock ready

Bit 0 – INTCLKEN Internal Clock Enable

This bit is set to 0 when the peripheral is not used or is awaiting a wakeup interrupt. In this case, its internal clock is stopped to reach a very low power state. Registers are still able to be read and written. The clock starts to oscillate when this bit is set to 1. Once the clock oscillation is stable, the peripheral sets Internal Clock Stable (INTCLKS) in this register to 1.

ValueDescription
0

The internal clock stops.

1

The internal clock oscillates.