40.8.34 SDHC Host Controller Version Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | HCVR |
| Offset: | 0xFE |
| Reset: | 0x1802 |
| Property: | - |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| VVER[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SVER[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | |
Bits 15:8 – VVER[7:0] Vendor Version Number
Reserved. Value subject to change. No functionality associated.
Bits 7:0 – SVER[7:0] Specification Version Number
This status indicates the SD Host Controller Specification Version.
| Value | Name |
|---|---|
| 0 | SD Host Specification Version 1.00 |
| 1 | SD Host Specification Version 2.00, including the feature of the ADMA and Test Register |
| 2 | SD Host Specification Version 3.00 |