40.8.38 SDHC AHB Control Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | ACR |
| Offset: | 0x208 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| B1KBDIS | HNBRDIS | BMAX[1:0] | |||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bit 5 – B1KBDIS 1kB Boundary Disable
Only significant when the xKBBoundary is not supported by the HMATRIX. Used for debug.
Bit 4 – HNBRDIS HNBREQ Disable
Used for debug to modulate the peripheral host interface bandwidth. Set to 1 to reduce the peripheral bandwidth.
Bits 1:0 – BMAX[1:0] AHB Maximum Burst
This field selects the maximum burst size in case of DMA transfer.
| Value | Name | Description |
|---|---|---|
| 0 | INCR16 |
The maximum burst size is INCR16. |
| 1 | INCR8 |
The maximum burst size is INCR8. |
| 2 | INCR4 |
The maximum burst size is INCR4. |
| 3 | SINGLE |
Only SINGLE transfers are performed. |