40.8.11 SDHC Power Control Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | PCR |
| Offset: | 0x29 |
| Reset: | 0x0E |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SDBPWR | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bit 0 – SDBPWR SD Bus Power
This bit is automatically cleared by the peripheral if the card is removed. If this bit is cleared, the peripheral stops driving SDHC_CMD and SDHC_DAT[7:0] (tri-state) and drives SDHC_CK to low level.