35.6.7.10 DMA, Interrupts, and Events
| CONDITION | REQUEST | ||
|---|---|---|---|
| DMA | INTERRUPT | EVENT | |
| Standard (DRE): Data Register
Empty FIFO (DRE): at least TXTRHOLD locations in TX FIFO are empty | Yes (Request cleared when data is written) | Yes | N/A |
| Standard (RXC): Receive Complete FIFO (RXC): at least RXTRHOLD data available in RX FIFO, or a last word available and length frame reception completed. | Yes (Request cleared when data is read) | Yes | |
| Standard (TXC): Transmit Complete FIFO (TXC): Transmit Complete and TX FIFO is empty | N/A | Yes | |
| Receive Start (RXS) | N/A | Yes | |
| Clear to Send Input Change (CTSIC) | N/A | Yes | |
| Receive Break (RXBRK) | N/A | Yes | |
| Error (ERROR) | N/A | Yes | |
DMA Operation
The USART generates the following DMA requests:
- Data received (RXC): The request is set when data is available in the receive FIFO or if at least RXTRHOLD data are available in the RX FIFO when FIFO operation is enabled. The request is cleared when DATA is read.
- Data transmit register empty (DRE): The request is set when the transmit buffer (TX DATA) is empty or if at least TXTRHOLD data locations are empty in the TX FIFO, when FIFO operation is enabled. The request is cleared when DATA is written.
Interrupts
The USART has the following interrupt sources. These are asynchronous interrupts, and can wake-up the device from any Sleep mode:
- Data Register Empty (DRE)
- Receive Complete (RXC)
- Transmit Complete (TXC)
- Receive Start (RXS)
- Clear to Send Input Change (CTSIC)
- Received Break (RXBRK)
- Error (ERROR)
Each interrupt source has its own Interrupt flag. The Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) will be set when the Interrupt condition is met. Each interrupt can be individually enabled by writing '1' to the corresponding bit in the Interrupt Enable Set register (INTENSET) and disabled by writing '1' to the corresponding bit in the Interrupt Enable Clear register (INTENCLR).
An interrupt request is generated when the Interrupt flag is set and if the corresponding interrupt is enabled. The interrupt request remains active until either the Interrupt flag is cleared, the interrupt is disabled, or the USART is reset. For details on clearing Interrupt flags, refer to the INTFLAG register description.
The value of INTFLAG indicates which interrupt is executed. Note that interrupts must be globally enabled for interrupt requests. Refer to the Nested Vector Interrupt Controller for details.