35.6.7.12 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers must be synchronized when written or read.

The following bits are synchronized when written:

  • The Software Reset bit in the Control A register (CTRLA.SWRST)
  • The Enable bit in the Control A register (CTRLA.ENABLE)
  • The Receiver Enable bit in the Control B register (CTRLB.RXEN)
  • The Transmitter Enable bit in the Control B register (CTRLB.TXEN)
Note:
  1. Required write synchronization is denoted by the "Write-Synchronized" property in the register description. If a write-synchronized register is written while a synchronization is ongoing, an APB error will be generated.
  2. CTRLB.RXEN is write-synchronized somewhat differently. For additional information, refer to the CTRLB.RXEN bit description.