35.6.8 USART Register Summary

Registers can be 8, 16, or 32 bits wide. Atomic 8, 16, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.

Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-Synchronized" and/or "Write-Synchronized" property in each individual register description.

Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write Protection" property in each individual register description.

Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable protection is denoted by the "Enable-Protected" property in each individual register description.

On devices with TrustZone support, this peripheral has different access permissions depending on Security Attribution (Secure or Non-Secure):

• If the peripheral is configured as non-Secure:
  • Secure access and non-Secure access are granted
• If the peripheral is configured as Secure:
  • Secure access is granted
  • Non-Secure access is discarded (Write is ignored, read 0x0) and a PAC error is triggered

Refer to Peripherals Security Attribution for more information.

For descriptions and definitions of both Register and bitfield properties, refer to Register Properties.