35.6.7.2 SERCOM USART Basic Operation

The following registers are enable-protected, meaning they can only be written when the USART is disabled (USART - CTRLA.ENABLE = 0):

• The Control A register (USART - CTRLA), except the Enable (ENABLE) and Software Reset (SWRST) bits.
• The Control B register (USART - CTRLB), except the Receiver Enable (RXEN) and Transmitter Enable (TXEN) bits.
• The Baud register (BAUD).

When the USART is enabled or is being enabled (USART - CTRLA.ENABLE = 1), any writing attempt to these registers will be discarded. If the peripheral is being disabled, writing to these registers will be executed after disabling is completed.

Enable-protection is denoted by the "Enable-Protection" property in the register description.

Before enabling the USART, it must be configured using the following steps:

1. Select either external (USART - CTRLA.MODE = 0x0) or internal clock (USART - CTRLA.MODE = 0x1).
2. Select either Asynchronous (0) or Synchronous (1) Communication mode by writing the Communication Mode.
3. Bit in the USART - CTRLA.CMODE register.
4. Select pin for receive data by writing the Receive Data Pinout value in the USART - CTRLA.RXPO register.
5. Select pads for the transmitter and external clock by writing the Transmit Data Pinout bit in the USART - CTRLA.TXPO register.
6. Configure the Character Size field in the USART - CTRLB.CHSIZE register for character size.
7. Set the Data Order bit in the USART - CTRLA.DORD register to determine MSB or LSB-first data transmission.
8. To use parity mode:
   1. Enable Parity mode by writing 0x1 to the Frame Format field in the USART - CTRLA.FORM register.
   2. Configure the Parity Mode bit in the USART - CTRLB.PMODE register for even or odd parity.
9. Configure the number of stop bits in the Stop Bit Mode bit in the USART - CTRLB.SBMODE register.
10. When using an internal clock, USART - CTRLA.MODE = 0x1, write the Baud register (BAUD) to generate the desired baud rate.
11. Enable the transmitter and receiver by writing '1' to the USART - CTRLB.TXEN and USART - CTRLB.RXEN enable bits in the USART - CTRLB register.

For both Synchronous and Asynchronous modes, the clock used for shifting and sampling data can be generated internally by the SERCOM baud-rate generator or supplied externally through the XCK line.

The Synchronous mode is selected by writing to the Communication Mode bit in the USART - CTRLA.CMODE = 1 register bit.

Asynchronous mode is selected by writing USART - CTRLA.CMODE = 0.

The internal clock source is selected by writing USART - CTRLA.MODE = 1 register bit.

The external clock source is selected by writing USART - CTRLA.MODE = 0 register bit.

The SERCOM Baud Rate Generator is configured as shown in Synchronous Mode XCK Timing.

In Synchronous mode, the CTRLA.MODE bit field determines whether the transmission clock line (XCK) serves either as input or output. The dependency between clock edges, data sampling, and data change is the same for internal and external clocks. Data input on the RxD pin is sampled at the opposite XCK clock edge when data is driven on the TxD pin.

The Clock Polarity bit in the Control A register (CTRLA.CPOL) selects which XCK clock edge is used for RxD sampling, and which is used for TxD change:

• When CTRLA.CPOL is '0', the data will be changed on the rising edge of XCK and sampled on the falling edge of XCK.
• When CTRLA.CPOL is '1', the data will be changed on the falling edge of XCK and sampled on the rising edge of XCK.

When the external clock input is provided through XCK (CTRLA.MODE = 0x0), the RX and TX shift registers operate directly on the XCK clock. This means that XCK is not synchronized with the system clock and, therefore, can operate at frequencies up to 1 / [(3 * T_RISE I/O) + (3 *T_FALL I/O))]. In Synchronous mode, no matter XCK clock is input or output, is always continuous, regardless of if no data is being transmitted or received.

The USART Transmit Data register (TxDATA) and USART Receive Data register (RxDATA) share the same I/O address, referred to as the Data register (DATA). Writing the DATA register will update the TxDATA register. Reading the DATA register will return the contents of the RxDATA register.

Data transmission is initiated by writing the data to be sent into the DATA register. Then, the data in TxDATA will be moved to the Shift register when the Shift register is empty and ready to send a new frame. After the Shift register is loaded with data, the data frame will be transmitted.

When the entire data frame including Stop bit has been transmitted and no new data was written to DATA, the Transmit Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.TXC) will be set, and the optional interrupt will be generated.

Depending on the value of CTRLC.FIFOEN, the Data Register Empty flag in the Interrupt Flag Status and Clear register (INTFLAG.DRE) indicates either:

1. If CTRLC.FIFOEN = 1, then at a minimum, (CTRLC.TXTRHOLD), FIFO threshold locations are empty and ready for new data, INTFLAG.DRE = 1.
2. If CTRLC.FIFOEN = 0, then the DATA register is ready to accept new TxDATA, INTFLAG.DRE = 1.

Disabling the Transmitter

The transmitter is disabled by writing '0' to the Transmitter Enable bit register (CTRLB.TXEN).

Disabling the transmitter will not take effect until after any ongoing and pending transmissions are completed, INTFLAG.TXC = 1.

The receiver accepts data when a valid Start bit is detected. Each bit following the Start bit will be sampled in asynchronous mode according to ((CTRLA.SAMPR = 3, 8, 16) * baud rate) or in synchronous mode according to XCK clock and shifted into the receive Shift register until the first Stop bit of a frame is received. The second Stop bit will be ignored by the receiver. When the first Stop bit is received and a complete serial frame is present in the Receive Shift register, the contents of the Shift register will be moved into the receive buffer.

If CTRLC.FIFOEN = 1, when the number of bytes present in the FIFO equals or is higher than the threshold value defined by the CTRLC.RXTRHOLD setting the Receive Complete Interrupt flag in the Interrupt Flag Status register, (INTFLAG.RXC), will be set: An optional interrupt will be generated if INTENSET.RXC = 1. The user can continue to read the DATA register as long as INTFLAG.RXC =1 until the FIFO is empty and INTFLAG.RXC = 0.

If CTRLC.FIFOEN = 0, the Receive Complete Interrupt flag in the Interrupt Flag Status register, (INTFLAG.RXC), will be set: An optional interrupt will be generated if INTENSET.RXC = 1. The user can read the received data from the DATA register until INTFLAG.RXC = 0.

Disabling the Receiver

Writing '0' to the Receiver Enable bit in the CTRLB register (CTRLB.RXEN) will disable the receiver, flush the two-level receive buffer, and data from ongoing receptions will be lost.

Error Bits

The USART receiver has three error bits in the Status (STATUS) register: Frame Error (FERR), Buffer Overflow (BUFOVF), and Parity Error (PERR). Once an error happens, the corresponding error bit will be set until it is cleared by writing ‘1’ to it. These bits are also cleared automatically when the receiver is disabled.

On any error, (STATUS.ERROR = 1), the USART transmit and receive operations are halted until the DATA register is read and emptied, INTFLAG.RXC = 0, by the user software followed after by the user clearing all the corresponding STATUS register error bits. Subsequent data received after the initial error is lost until the error conditions are resolved and normal operation can resume.

There are two methods for buffer overflow notification, selected by the Immediate Buffer Overflow Notification bit in the Control A register (CTRLA.IBON):

• When CTRLA.IBON = 1, STATUS.BUFOVF is raised immediately upon buffer overflow. Software can then empty the receive FIFO by reading the DATA register, until the Receiver Complete Interrupt flag (INTFLAG.RXC) is cleared.
• When CTRLA.IBON = 0, the Buffer Overflow condition is attending data through the receive FIFO. After the received data is read, STATUS.BUFOVF will be set along with INTFLAG.RXC.

Asynchronous Data Reception

The USART includes a clock recovery and data recovery unit for handling asynchronous data reception.

The clock recovery logic can synchronize the incoming asynchronous serial frames at the RxD pin to the internally generated baud-rate clock. The data recovery logic samples and applies a low-pass filter to each incoming bit, thereby improving the noise immunity of the receiver.

Asynchronous Operational Range

The operational range of the asynchronous reception depends on the difference between the internal baud-rate clock frequency of the receiving device relative to the internal baud rate frequency of the remote transmitting device, (i.e., baud rate error). The maximum baud rate error should exceed ±1.5% for any individual serial device in the network for a total error between devices not to exceed ±3%. The ±3% maximum error assumes that the receiver and transmitter equally divide the ±3% maximum total error for ±1.5% for each USART device.

Error % = [(1 – (Expected Baud Rate / Actual Baud Rate)) * 100]