1.4.4 Transceiver Clock Regions

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Two regional clock buffers per transceiver lane (eight per transceiver quad) come from the transceiver. These interconnections are the basis for specific regions that the particular quads can drive. These regions vary from device to device within the family. These regions have a predetermined connectivity to fabric resources, CCC, and I/Os.

Figure 1-36. PolarFire® and RT PolarFire FPGA Transceiver Clock Regions

Figure 1-37. PolarFire® SoC FPGA Transceiver Clock Regions

Users need to understand the regional clock implications when targeting designs that may migrate to different device sizes. The user must also use this in pin planning of boards when desiring to drive I/O from the transceiver clocks.

Table 1-13. PolarFire® and RT PolarFire FPGA Clock Region Connectivity
Device	Region	FPGA Fabric Resource Count
		IO	4LUT	DFF	MATH	SRAM	URAM	CCC (PLL/DLL) (CCC_NE, CCC_SE)
MPF100T	One Only	120	49260	49260	152	160	456	4(PLL/DLL) (CCC_NE, CCC_SE)
MPF200T	Top	60	49980	49980	152	160	456	2- CCC (PLL/DLL) (CCC_SE)
MPF200T	Bottom	60	37296	37296	114	120	342	2- CCC (PLL/DLL) (CCC_SE)
MPF300T	Top	96	80652	80652	248	256	744	2- CCC (PLL/DLL) (CCC_NE)
MPF300T	Bottom	96	60192	60192	186	192	558	2- CCC (PLL/DLL) (CCC_SE)
MPF500T/RTPF500	Top	120	75468	75468	234	240	702	2- CCC (PLL/DLL) (CCC_NE)
	Middle	0	102516	102516	312	320	936	0
	Bottom	120	75468	75468	234	240	702	2- CCC (PLL/DLL) (CCC_SE)

Table 1-14. PolarFire® SoC FPGA Clock Region Connectivity
Device	Region	FPGA Fabric Resource Count
		IO	4LUT	DFF	MATH	SRAM	URAM	CCC (PLL/DLL) (CCC_NE, CCC_SE)
MPFS250T	Top	96	80652	80652	248	256	744	2- CCC (PLL/DLL) (CCC_NE)
MPFS250T	Bottom	96	60192	60192	186	192	558	2- CCC (PLL/DLL) (CCC_SE)

See PolarFire Family Clocking Resources User Guide for more information about regional clock resource regions.