1.4.6 Transceiver Clocking Use Cases

Each transceiver quad can source a global clock directly. Transceiver designs should use regional clocks for the interface logic when possible. This reduces over use of global clocks. In many cases, transceiver designs can share global clocks when multiple interfaces are used, depending on protocol requirements. Only one global clock is supported per transceiver quad. See respective PolarFire FPGA Datasheet , RT PolarFire FPGA Datasheet, or PolarFire SoC Datasheet for AC performance information. For information about connectivity of the transceivers to the global clock network, see PolarFire Family Clocking Resources User Guide.

The following table lists the transceiver interface clocking use cases in the Libero SoC software, which uses presets per protocol. See PCS/FPGA Fabric Interface for explanation of system clock source modes.

Table 1-16. Transceiver Interface Clocking Use Cases
PresetWidthRxTx1System Clock Source1
10GBASE-Rx1RegionalGlobalGlobal from XCVR Tx
10GBASE-RMultipleRegionalGlobal sharedGlobal from XCVR Tx shared
10GBASE-KRx1 and MultipleRegionalRegional
SGMII/1000BASEx1RegionalRegionalGlobal from XCVR Tx
SGMII/1000BASEMultipleRegionalGlobal sharedGlobal from XCVR Tx shared
JESD204Bx1RegionalGlobalGlobal from XCVR Tx shared
JESD204BxNRegionalGlobal sharedGlobal from XCVR Tx shared
CPRIx1RegionalRegionalGlobal
CPRIxNRegionalRegionalGlobal shared
InterlakenxNRegional ≥ Global2Global sharedGlobal from XCVR Tx shared
XAUIx4RegionalGlobal sharedGlobal from XCVR Tx shared
RXAUIx2RegionalGlobal sharedGlobal from XCVR Tx shared
SDI3x1GlobalGlobalGlobal
SDI3MultipleGlobalGlobal sharedGlobal
LiteFast3x1GlobalGlobalGlobal from XCVR Tx and Rx
LiteFast3xNRegional ≥ Global2Global sharedGlobal from XCVR Tx (shared) and Rx
LiteFast3x1 and MultipleGlobalGlobal sharedGlobal from XCVR Tx (shared) and Rx (per interface)
QSGMIIx1RegionalRegionalGlobal 125 MHz
QSGMIIMultipleRegionalGlobal sharedGlobal 125 MHz Shared
SATA3x1Global TxGlobal TxGlobal Tx
SATA3MultipleGlobal TxGlobal TxGlobal Tx (not shared)
SRIOx1RegionalGlobalGlobal
SRIOxNRegionalGlobal sharedGlobal
SRIOMultipleRegionalGlobal (per interface)Global
Fiber Channelx1RegionalGlobal TxGlobal Tx
Fiber ChannelMultipleRegionalGlobal Tx sharedGlobal Tx Shared
(1) Shared implies that multiple lanes use common clock resources.

(2) Uses regional clock and moves to global clock resources in the FPGA fabric.

(3) Typically, these interfaces are implemented uni-directional. For full duplex, the RX interface and TX interface clock can not be global or global (Shared) at the same time as only one global clock is supported per transceiver quad. If using the RX and TX both as global is required by design, the design must use two separate XCVR configurations (instances), one in RX half duplex mode and other in TX half duplex mode.