1.4.1 Non-Deterministic Interface

The transceiver PMA to FPGA fabric/PCS data path includes a fly-wheel FIFO (FWF) interface, which is used to transfer data between clock domains. This interface is included within the protocol-specific PCS HDL modules or user FPGA fabric logic.

FWF is a simple form of FIFO where its write and read clocks are known to be at the same nominal frequency, with some allowed phase difference and jitter that is compensated within the block.

The interface between the PMA and fabric cannot be throttled. However, the addition of the FWF block in the data path handles the phase crossing of every PMA lane, ensuring that timing is met across this interface. The received data, along with the recovered parallel clock, is passed to the FWF, which synchronizes the data and clock for either regional or global clock routing.

In the transmit direction, data from the fabric or PCS is passed through the FWF with a clock from the FWF ensuring synchronous clock and data relationships passing to the PMA interface. The FWF is optionally selected in the Libero Transceiver Configurator by choosing the correct global or regional interface clock option, see Table 2-8.

Figure 1-30. Non-Deterministic Interface With FWF

The FWF provides clock domain crossing functionality to manage clock and data setup and hold. The following figures show the timing relationships of transmit and receive data paths at the fabric interface.

Figure 1-31. Non-Deterministic Interface Transmit Timing Waveform
Figure 1-32. Non-Deterministic Transceiver Receive Timing Waveform