1.4.5 Transceiver Data Path Latency

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Transceiver data path latency is defined, when the earliest serial bit appears in bus bit 0 for both transmit and receive interfaces of PMA mode. The PMA mode data path can be setup for different transmit and receive widths as needed. Clock phase latency is not considered.

Table 1-15. Transceiver Data Path Latency
PCS Mode	PCS Fabric Width	PMA PCS Width	Transmit Latency (UI)	Receive Latency (UI)
PMA	8	8	82	58.5
PMA	10	10	100	73.4
PMA	16	16	148	122.4
PMA	20	20	184	153.6
PMA	32	32¹	292	250.5
PMA	40	40	364	313.5
PMA	64	32¹	452	410.5
PMA	80	40	564	513.5
8b10b	40	40	404	314
8b10b	80	40	564	513.5

Note:

Use 32-bit PMA latency for minimum 64b66b latency. Maximum 64b66b latency calculation is described in 64b66b Latency Considerations.

Important: 8b10b mode uses 20, 40, and 80 PmaPcsWidth. PIPE modes uses 40 PmaPcsWidth.