1.4.2 Deterministic Interface
(Ask a Question)Low-latency regional clocks with a specific mode of the FWF are used when a zero-cycle path is required. For example, by protocols such as CPRI and JESD204B that require both receive and transmit paths have a fixed deterministic latency as expressed in number of clock cycles. In this case, data is interfaced directly to capture registers while the clock is routed on regional clock resources. The regional clock does not have the large clock insertion delay as the global clock network. A regional clock can easily achieve timing closure to the fabric with this small amount of clock delay. Deterministic timing is optionally selected in the Libero Transceiver configurator by choosing the deterministic regional options, see Table 2-8.
