1.4.3 Interface Latency

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Latency of a FWF is half of its depth with an uncertainty of 1. The Deterministic mode for the FWF has a pipeline stage added between the fabric and the FWF due to which the latency is higher for this mode. This means that the Non-Deterministic (phase-compensating) mode has less latency because it bypasses the extra pipeline stage.

FWF is 8-deep for both Deterministic (± 1) and Non-Deterministic modes. The Non-Deterministic mode is controlled by the pcslane/lclk_r0/lclk_txfwf_tmg_mode register selected between Deterministic mode and the Phase Compensating mode. Deterministic mode is enabled when lclk_txfwf_tmg_mode is equal to 1.

Libero SoC software allows to select the Deterministic mode options within the Transceiver Interface configurator when selecting Tx and Rx clock options.