1.1.1.8 Receive PCS Divider

The PCS divider divides the bit-rate clock from the CDR PLL to a lower rate for use in the receive PCS. The PMA sends parallel data from the de-serializer up to 40-bits wide. This divider also sets the width of the parallel data provided to the PCS to 8, 10, 16, 20, 32, 40, 64, or 80 bits. The Libero transceiver configurator sets the divider based on the data rate and ultimate fabric interface width.