1.1.1.1 Receive Input Buffer

The receiver provides an external input interface through differential pins, XCVR_RXP/N, as shown in the following figure. The receiver includes a current mode logic (CML) input buffer with programmable DC restoration that is used in either AC- or DC-coupled applications.

The receive buffer provides an on-die differential termination scheme which can be programmed to 85Ω, 100Ω, or 150Ω. The receiver buffer also includes a high-impedance (high-Z) mode for hot-swap capability when the device is powered OFF. Additionally, the receiver input supports logical swapping of the polarity of the P and N pins for added flexibility.

Figure 1-2. Receiver Input Buffer
Important: VICM is connected to VDDA when AC-coupled link is configured. DC-coupled configurations effectively disconnects VICM source. See AC/DC Coupled Connection.

Each receiver lane includes optional signal threshold detection circuitry that users can select according to protocol or application requirements. This feature identifies whether the signal level present at the receiver input buffer is above the signal detect threshold voltage needed to trip or activate the receiver input, which prevents false activity on the receiver path. The signal detection has both a high and low signal detector. The Libero SoC software configurator provides the correct setting based on protocol or customization.

Important: The user can also use a JTAG-based interface from SmartDebug to experiment with receiver settings.