3.5.1.19.3 Pointer Argument Driver Functions

For each pointer (including array, struct types) argument that is configured to use AXI4 target interface (see 3.5.1.18.3.3 AXI4 Target Interface), the following driver functions will be provided:

// 'memcpy' driver functions:
// The processor performs memory-mapped write/read operations (using the standard memcpy function) to copy data between the memory at 'MyPtrArg' and the HLS accelerator.
// The total size to transfer is defined by the 'byte_size' argument.
void MyTopFunc_memcpy_write_MyPtrArg(void* MyPtrArg, uint64_t byte_size);
void MyTopFunc_memcpy_read_MyPtrArg (void* MyPtrArg, uint64_t byte_size);

// 'dma' driver functions:
// The processor offloads the data transfer to a DMA engine to move data between the memory at 'MyPtrArg' and the HLS accelerator.
// The total size to transfer is defined by the 'byte_size' argument.
void MyTopFunc_dma_write_MyPtrArg(void* MyPtrArg, uint64_t byte_size);
void MyTopFunc_dma_read_MyPtrArg (void* MyPtrArg, uint64_t byte_size);

The DMA driver functions can use one of two different DMA engines depending on the target FPGA family and HLS project settings. Note that when the HLS project's target flow is set to Icicle_SoC (see 3.6.2.2.7 set_project), SmartHLS™ by default uses the harden platform DMA (PDMA) engine in the Microprocessor Sub-System (MSS). In this case, the DMA driver functions are expected to run on a Linux Operating System (see Step 5: Flashing the Linux Image to the Board), and the processor memory referenced by the pointer argument (MyPtrArg) must be allocated by the hls_malloc function (see Memory Allocation Library). On PolarFire® SoC devices, it is recommended to use the PDMA engine for data transfer when the transfer size is equal to or bigger than 16KB, and use the memcpy driver functions when the transfer size is smaller than 16KB.

When targeting other device families,SmartHLS assumes a soft CoreAXI4DMAController IP (implemented in FPGA Fabric) is connected with the processor memory and the HLS accelerator's AXI4 target interface. In this case, the DMA_BASE_ADDR macro in the accelerator driver header file (i.e., hls_output/accelerator_drivers/<PROJ_NAME>_accelerator_driver.h) should be updated to the base address of the DMA IP's AXI4-lite control interface.